The trend in semiconductor memory devices is to constantly produce devices having more memory and/or having a smaller die size. For example, the cost of producing a semiconductor memory device, such as a Flash memory device having one or more bits in each memory cell can be reduced by reducing the size of the flash memory device die size. Typically the reduction of Flash memory device die size is accomplished by investing in a next technology lithography node. However, such investment is costly in terms of research and developments costs and time.
Conventional Flash memory devices include a plurality of memory core arrays, each memory core array including a predetermined number of memory cells for nonvolatilely storing one or more bits of information. Each of the plurality of memory core arrays includes a bitline decoder, a decoding circuit that includes arrays of sector select (SSEL) transistors. The array of SSEL transistors consumes a large amount of die space.
Thus, it is desirable to provide a method and apparatus for performing one or more memory operations which would allow for reduction in the Flash memory device die size by reducing the size of the SSEL transistors while improving their performance without changing the fabrication process of the Flash memory device or increasing the production cost thereof. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.